In digital data communication systems the transmission of data, from a transmitter circuit to a receiver circuit, requires timing information in order to properly interpret the received data. These data communication systems operate in either a synchronous or asynchronous mode.
In the synchronous mode signal transitions and timing occur at integral multiples of the bit length. Thus, the synchronous data signal source typically generates data words having a fixed length and fixed spacing between consecutive data words. In synchronous systems the timing information is conveyed to the receiver circuit by the data signal transitions, by sending one or more specific codes or by clock signals sent with the data transmission to the receiver circuit. The receiver circuit adjusts its synchronization circuits using this timing information to insure that the received signal is sampled when the data is in a stabilized state rather than when it is in a transition state. Thus, in these synchronous digital systems, all the data word timing and signal transitions occur in integer multiples of the bit time.
In asynchronous digital systems the data signal source typically generates data words in which the bit timing is asynchronous or synchronous within the data word and is asynchronous between the data words. Thus, the data words start at a non-uniform interval of time resulting in irregular spacing between consecutive data words. In these asynchronous digital systems the data word timing is preserved by utilizing extra bits, such as start bits, which are added to each data word to enable the synchronization of the receiver circuit to the received digital data. In other asynchronous data devices the protocol, the relative timing between the start bit and the data bits of the data signals, must be preserved during a data transmission. In this type of asynchronous device both the length of the data word as well as the spacing between consecutive data words are irregular. Thus, the preservation of the timing of data transmissions between such asynchronous devices becomes even more critical.
In digital communication systems which interconnect with both synchronous and asynchronous data devices it is required to provide a separate interface for each application. Thus it is a problem to provide one interface circuit in a digital communications system which can communicate both synchronous and asynchronous data signals.
Prior art communication arrangements include a method of transmitting asynchronous data bits in a synchronized data stream. For example, U.S. Pat. No. 3,748,393 issued to J. V. Baxter on July 24, 1973 discloses an arrangement for substituting asynchronous data bits for one data channel of a transmitted data bit stream. In the Baxter arrangement the location of a marker bit is utilized to indicate the number and repetition rate of the inserted asynchronous data bits. The Baxter patent, however, does not preserve the protocol timing of the asynchronous data signal.
In another arrangement, U.S. Pat. No. 3,723,657 issued to H. Muller on Mar. 27, 1973, a time multiplex transmission process maintains the transition timing as disclosed which is data signals up to a maximum transmission rate. In the Muller patent a sample of the binary data signal is transmitted at the maximum transmission rate of the system. In between data samples a counter counts the elapsed time from the previous transmitted sample of the binary signal. When a transition in the binary state of the signal occurs, the existing count of the counter is transmitted immediately after the next sample indicating when the change of state of the binary signal occurred. Thus, the receiver can determine, from the received counter data, the exact time between the samples when the signal changed binary state. The Muller patent, however, does not teach how to simultaneously transmit synchronous and asynchronous data signals over a data communication facility.
Thus, it is an existing problem in the art to design a data communication arrangement which simultaneously transmits asynchronous and synchronous data signals over a data facility and which is transparent to the timing of the asynchronous data signals.